In a fabrication of semiconductor devices, IC designs and resulting devices may need an e-fuse to allow programming (e.g., “blow a fuse”) for digital information storage in a resulting IC. Typical e-fuse structures include a 2-terminal resistor using doped polysilicon in gate first high-k metal gate (HKMG) fabrication methods or silicide or thin metal for gate last HKMG processes for advanced complementary metal-oxide semiconductor (CMOS) nodes at the 28 nm technology node or beyond. However, processes to fabricate and program a 2-terminal resistor e-fuse typically require an extra mask, resulting in extra complexity and expense. Moreover, the size of 2-terminal resistors in an IC may be greater than an order of magnitude larger in size relative to CMOS transistors of the IC design. As such, adding a 2-terminal resistor array in CMOS circuit requires a large Si area and reduces a density of features of an IC design. Further, the operating voltage/current to blow or program the e-fuse is often large (˜5×) compared to a typical logic circuit operating voltage (Vcc) (e.g. Vcc˜1v to 1.2v at 28 nm CMOS node). Thus, an e-fuse with a select transistor (for selecting a specific e-fuse to be blown or programmed) can form a one-time programming (OTP) cell with programming that requires either an external high voltage source or a charge pump circuit to generate, on-chip, a higher voltage than Vcc.
A need therefore exists for methodology compatible with CMOS flow enabling fabrication of a smaller e-fuse and OTP with a low programming voltage/current, and the resulting device.